The present invention relates to a method to transit in a communication system from a low power state to a full power state, an arrangement to be used to transit from the low power state to the full power state in a transmitter and an arrangement to transit from the low power state to the full power state in a receiver.
Such a state transition method and arrangement to perform such a state transition are already known in the art, e.g. from the temporary document WH-031 submitted on Jun. 29, 1998 to ITU Study Group 15 which is an ADSL (Asymmetric Digital Subscriber Line) forum. This document with reference WH-031 is entitled ‘Time Domain Rate Adaptation Based L1 State for C. Lite Modem Power Down Management’ and originates from IteX. In this document, a mechanism for transition between a so called L1 state, a low power/low bit rate state, to a so called L0 state, a full power/full bit rate state, of an ADSL (Asymmetric Digital Subscriber Line) system is described. AS is indicated in paragraph 2 of the cited document, transition between the low power and the full power state is initiated by transfer of a predetermined recognizable state transition indication, called EOC message. Thereafter, the new state is entered at the beginning of the next super-frame. The transition time to switch from the low power state to the full power state is not minimized in the known solution because the actual transition from the low power state to the full power state is delayed until the beginning of the next super-frame. In particular systems such as the known one, wherein data are transferred at a low bit rate during the low power state, the transition time can become significantly large, i.e. several multiples of the time interval required to transfer a super-frame at full power. In communication systems with buffers temporarily storing data, large state transition times imply increased probability for buffer overflow, congestion and even loss of data. If for instance ATM (Asynchronous Transfer Mode) cells have to be transferred over an ADSL (Asymmetric Digital Subscriber Line) network segment, risk of ATM buffer overflow increases if the wake-up time, i.e. the transition time from the low power state to the full power state of the ADSL network segment is large.